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Secure FPGA Circuits Using Controlled Placement and Routing
Pengyuan Yu, Patrick Schaumont,
CODES+ISSS 2007
Abstract:
In current Field-Programmable-Logic Architecture (FPGA) design flows, it is very hard to control the routing of submodules. It is thus very hard to make an identical copy of an existing circuit within the same FPGA fabric. We have solved this problem in a way that still enables us to modify the logic function of the copied sub-module. Our technique has important applications in the design of side-channel resistant implementations in FPGA. Starting from an existing single-ended design, we are able to create a complementary circuit. The resulting overall circuit strongly reduces the power-consumption-dependent information leaks. We show that the direct mapping of a secure ASIC circuit-style in an FPGA does not preserve the same level of security, unless our symmetrical routing technique is employed. We demonstrate our approach on an FPGA prototype of a cryptographic design, and show through power-measurements followed by side-channel power analysis that secure logic implemented with our approach is resistant whereas non-routing-aware directly mapped circuits can be successfully attacked.
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Implementation of DPA-Resistant Circuit for FPGA
      Pengyuan Yu     - MS THESIS - 2007
Comments About Paper
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با سلام :پاسخ سوالات به شرح زیر می باشد :1 . تعداد کل LSA Type-1 در دیتابیس روتر R3 سه عدد می باشد، که به شرح زیر است :Link ID ADV Router2.2.2 6/1/2012 3:14:16 AM
 -  با سلام :پاسخ سوالات به شرح زیر می باشد :1 . تعداد کل LSA Type-1 در دیتابیس روتر R3 سه عدد می باشد، که به شرح زیر است :Link ID ADV Router2.2.2.2 2.2.2.23.3.3.3 3.3.3.37.7.7.7 7.7.7.72 . تعداد کل لینک ها در OSPF Database روی R3 یک عدد می باشد، که به شرح زیر است :Link ID ADV Router22.22.22.2 2.2.2.23 .R2#show ip ospf database roteur self-originate OSPF Router with ID (2.2.2.2) (Process ID 100) Router Link States (Area 0) LS age: 1366 Options: (No TOS-capability, DC) LS Type: Router Links Link State ID: 2.2.2.2 Advertising Router: 2.2.2.2 LS Seq Number: 80000005 Checksum: 0x5BC5 Length: 60 AS Boundary Router Number of Links: 3 Link connected to: another Router (point-to-point) (Link ID) Neighboring Router ID: 3.3.3.3 (Link Data) Router Interface address: 33.33.33.2 Number of TOS metrics: 0 TOS 0 Metrics: 64 Link connected to: a Stub Network (Link ID) Network/subnet number: 33.33.33.0 (Link Data) Network Mask: 255.255.255.0 Number of TOS metrics: 0 TOS 0 Metrics: 64 Link connected to: a Transit Network (Link ID) Designated Router address: 22.22.22.2 (Link Data) Router Interface address: 22.22.22.2 Number of TOS metrics: 0 TOS 0 Metrics: 1R3#show ip ospf database roteur self-originate OSPF Router with ID (3.3.3.3) (Process ID 100) Router Link States (Area 0) LS age: 1489 Options: (No TOS-capability, DC) LS Type: Router Links Link State ID: 3.3.3.3 Advertising Router: 3.3.3.3 LS Seq Number: 80000006 Checksum: 0x387B Length: 48 AS Boundary Router Number of Links: 2 Link connected to: another Router (point-to-point) (Link ID) Neighboring Router ID: 2.2.2.2 (Link Data) Router Interface address: 33.33.33.3 Number of TOS metrics: 0 TOS 0 Metrics: 64 Link connected to: a Stub Network (Link ID) Network/subnet number: 33.33.33.0 (Link Data) Network Mask: 255.255.255.0 Number of TOS metrics: 0 TOS 0 Metrics: 64R7#show ip ospf database roteur self-originate OSPF Router with ID (7.7.7.7) (Process ID 100) Router Link States (Area 0) LS age: 1480 Options: (No TOS-capability, DC) LS Type: Router Links Link State ID: 7.7.7.7 Advertising Router: 7.7.7.7 LS Seq Number: 80000004 Checksum: 0xDC92 Length: 48 AS Boundary Router Number of Links: 2 Link connected to: a Stub Network (Link ID) Network/subnet number: 77.77.77.0 (Link Data) Network Mask: 255.255.255.0 Number of TOS metrics: 0 TOS 0 Metrics: 1 Link connected to: a Transit Network (Link ID) Designated Router address: 22.22.22.2 (Link Data) Router Interface address: 22.22.22.7 Number of TOS metrics: 0 TOS 0 Metrics: 1   
konrad 10/30/2007 8:22:29 AM
 -  Longer MS Thesis corresponding to paper: "Implementation of DPA-Resistant Circuit for FPGA"   
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