Side Channel Attacks Database
|
|
|
|
|
|
Secure and Efficient Use of Reconfigurable Hardware Devices in Symmetric Cryptography |
 |
|
|
Francois-Xavier Standaert, |
|
|
PhD THESIS 2004 |
|
| Abstract: |
|
Due to its potential to greatly accelerate a wide variety of applications,recon¯gurable computing has gained importance in the industrial development of digital signal processing. Recent devices such as Field Programmable Gate Arrays (FPGAs) can notably be used to deal with the high throughput constraints of video processing applications. They also constitute attractive options for the design of encryption algorithms. In this thesis, we investigate the secure and e±cient implementation of symmetric cryptographic algorithms in these recon¯gurable hardware devices.
At the implementation level, we demonstrate that good design rules adapted to devices and algorithms allow the hardware performances of symmetric-key block ciphers to be signi¯cantly improved. The resulting methodology is applied to the recently chosen (October 2000) Advanced Encryption Standard (AES) Rijndael.
At the application level, we analyze the possibility to use the high throughputs o®ered by hardware implementations to mount exhaustive key search attacks against encryption algorithms. We speci¯cally investigate a time-memory tradeo® attack using distinguished points and provide a detailed theoretical analysis of the di®erent attack parameters. At a more physical level, we question the feasibility of power analysis attacks in the context of recon¯gurable hardware devices. Based on simple hypotheses, we mount successful attacks against the two main
symmetric cryptographic standards, i.e. the Data Encryption Standard (DES) and the AES Rijndael. We also provide a general framework to evaluate a hardware design security with respect to power analysis. Finally, at the algorithmic level, we derive a list of potential improvements for block ciphers in terms of hardware implementation effciency and security against physical attacks. These observations are combined into the platform-speci¯c algorithm ICEBERG for which FPGA implementations exhibit better performances than most recent block ciphers. |
|
| Paper Available At: |
|
http://www.dice.ucl.ac.be/~fstandae/thesis_fxs.pdf |
|
|
|
|
|
|
|
|
|
|
|
|
Cited By: |
|
|
|
|
|
|
|
|
|
Sort: |
|
This paper has been referenced 0 times, showing 1-10 |
Page 1 of 0
|
|
|
|
|
|
|
|
|
|
|
|
| Comments About Paper |
|
|
|
|
| Post a Comment |
|
|
Enter the code shown:
|
| Name: |
|
| Email (optional) |
|
| Comment: |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| Direct any
comments, questions, omissions, criticizm here |
 |
|
|
|